The present invention relates to an analog-to-digital conversion circuit (referred to as an AD conversion circuit) of a successive approximation type having a sample-and-hold function. More specifically, the present invention relates to an AD conversion circuit, a micro-controller, and a method of adjusting a sampling time suitable for automatically adjusting a sampling time of an input value according to an input impedance that is changed depending on an external device connected thereto.
In general, a conventional AD conversion circuit having a sample-and-hold function is formed of a relatively simple circuitry configuration. Further, the conventional AD conversion circuit has a high compatibility with a COMS process capable of producing a circuit at a low cost, and tends to have a relatively small occupancy area. Accordingly, the conventional AD conversion circuit can be constituted by an LSI (Large Scale Integration), and is easy to be disposed in a micro-controller (MCU).
In the conventional AD conversion circuit, an analog input voltage is applied to a plurality of capacitor elements, so that electric charges corresponding to the analog input voltage are accumulated in each of the capacitor elements. As a result, the conventional AD conversion circuit is capable of holding a voltage corresponding to the electric charges thus accumulated. Then, the voltage is compared with an internal reference voltage of the conventional AD conversion circuit, so that the analog input voltage is output at a digital value associated with a resolution of the conventional AD conversion circuit.
It is noted that in the following description, the process of accumulating the electric charges corresponding to the analog input voltage into the capacitor elements is referred to simply as a process of charging the analog input voltage into the capacitor elements for the sake of a simple explanation.
In the conventional AD conversion circuit described above, in order to reduce the number of peripheral components, the capacitor elements, in which the analog input voltage is charged, may be disposed inside the conventional micro-controller, thereby constituting a conventional sample-and-hold circuit (referred to also as a conventional sample hold circuit).
A configuration and an operation of a conventional AD conversion circuit with six bits shown in FIG. 5 will be explained next. FIG. 5 is a circuit diagram showing an example of the configuration of the conventional AD conversion circuit.
As shown in FIG. 5, after an analog input voltage Vain is charged in an internal capacitor element array 1, a switch S1 is turned off, so that the analog input voltage Vain is separated from a C ladder 3. Afterward, the conventional AD conversion circuit starts an AD conversion operation (a conversion from an analog signal to a digital signal). When the conventional AD conversion circuit starts the AD conversion operation, a control circuit 2 formed of a digital log circuit controls switches SW1 to SW7 and a switch S4 to connect each of capacitor elements of the internal capacitor element array 1 to one of a reference voltage Vref and ground GND.
In the conventional AD conversion circuit, a convertor circuit 4 is connected to one end portion Cin of the internal capacitor element array 1, so that the convertor circuit 4 outputs a signal with a High level or a Low level according to a result of the AD conversion operation.
In the conventional AD conversion circuit, when the comparator circuit 4 performs the AD conversion operation, the control circuit 2 controls the comparator circuit 4 according to a reference clock signal CLK and a control signal transmitted from a micro-computer (not shown) disposed inside the LSI together with the conventional AD conversion circuit. After the comparator circuit 4 outputs to the control circuit 2, the control circuit 2 outputs the conversion result to the micro-computer.
In the conventional AD conversion circuit having the configuration described above, the internal capacitor element array 1 is capable of charging an electric charge Q as a whole, wherein the electric charge Q can be defined as follows:Q=64 pF×(Vt−Vain)where Vt is a threshold voltage of the comparator circuit 4. At this moment, the switch S1 for inputting the analog input voltage Vain and the switches S2 and S3 of the comparator circuit 4 are turned on (in the connected state).
After the charging period, the control circuit 2 controls the switch S1 for inputting the analog input voltage Vain and the switches S2 and S3 of the comparator circuit 4 to turn off (in the disconnected state). Accordingly, the internal capacitor element array 1 holds the electric charge Q until the comparator circuit 4 completes the AD conversion operation.
In the conventional AD conversion circuit, for example, when the comparator circuit 4 converts the highest bit through the AD conversion operation, only the capacitor element of 32 pF is connected to the side of the analog input voltage (or the reference voltage Vref) through the switch SW1, and other capacitor elements are connected to the ground GND through the switches SW2 to SW7 and the switch S4.
It should be noted that the conventional AD conversion circuit is capable of converting 10 bit (bit 9 to bit 0), and bit 9 is the highest bit. Accordingly, in the connection state described above, when a voltage V9 is applied to the one end portion Cin of the internal capacitor element array 1 (the side of the comparator circuit 4), since the electric charge Q accumulated in the internal capacitor element array 1 is maintained constant, the following equation (1) is established:Q=64 pF×(Vt−Vain)=32 pF×(V9−Vref)+32 pF×(V9−GND)  (1)
In the conventional AD conversion circuit, when a conversion voltage range is set from the power voltage VDD to the ground GND (0 V), that is, from the reference voltage Vref equal to the power voltage VDD (Vref=VDD) to the ground GND equal to 0 V (GND=0 V), a difference between the threshold voltage Vt and the voltage V9 (Vt−V9), which corresponds to a voltage variance at the one end portion Cin (an input portion) of the comparator circuit 4, is given as follows:Vt−V9=Vain−(½)×VDD 
In the conventional AD conversion circuit, the comparator circuit 4 is configured to determine the conversion result whether the voltage V9 is greater than the threshold voltage Vt. More specifically, when the analog input voltage Vain is greater than the half of the power voltage VDD (Vain>(½)×VDD), the voltage V9 is smaller than the threshold voltage Vt (V9<Vt), so that the conversion result is “1” (High). When the analog input voltage Vain is smaller than the half of the power voltage VDD (Vain<(½)×VDD), the voltage V9 is greater than the threshold voltage Vt (V9>Vt), so that the conversion result is “0” (Low).
Accordingly, in the conventional AD conversion circuit, the comparator circuit 4 is configured to determine the conversion result of the highest bit when the analog input voltage Vain is greater than the half of the power voltage VDD. It is noted that the comparator circuit 4 is configured to convert the other bit through the operation similar to that of the highest bit.
In the conventional AD conversion circuit having the configuration described above, however, when the analog input voltage Vain is charged in the internal capacitor element array 1, that it, when the input value is sampled, the following problems tend to occur.
For example, in the conventional AD conversion circuit, a period of time during which the analog input voltage Vain is sampled is determined by a time constant of the internal capacitor element array 1 and an input impedance of the conventional AD conversion circuit. Currently, in order to reduce the conversion time of the conventional AD conversion circuit, it has been tried to reduce the value of the input impedance. However, depending on the input impedance of the conventional AD conversion circuit, it may be difficult to secure a sufficient period of time during which the analog input voltage Vain is sampled. In this case, the conventional AD conversion circuit may output an erroneous conversion result. If this is the case, it is necessary to define the value of the input impedance.
However, in the conventional AD conversion circuit, the value of the input impedance is determined by an external device connected to the micro-controller that is provided with the conventional AD conversion circuit. Accordingly, it is difficult to determine the value of the input impedance on the side of the micro-controller unless the external device to be connected to the micro-controller is identified.
Alternatively, the value of the input impedance may be defined in advance as the specification thereof. In this case, it is difficult for a user to obtain desirable design flexibility. Further, it may be configured such that a plurality of sampling times is defined in advance, so that it is possible to select one of the sampling times. However, in order to configure the conventional AD conversion circuit as such, it is necessary to install a register and the like, thereby increasing a cost thereof.
Patent References 1 and 2 have disclosed conventional technologies relating to the sampling time in the conventional AD conversion circuits.
Patent Reference 1: Japanese Patent Publication No. 04-220016
Patent Reference 2: Japanese Patent Publication No. 07-264071
Patent Reference 1 has disclosed the conventional AD conversion circuit of a successive approximation type. The conventional AD conversion circuit disclosed in Patent Reference 1 includes an analog switch for controlling an input of an analog signal to be converted to a digital signal; a switch circuit portion to be used for sampling the analog signal; a capacitor element array portion formed of a plurality of capacitor elements weighed in a binary fashion; and a comparator portion for generating the digital signal as an output signal. Further, the conventional AD conversion circuit disclosed in Patent Reference 1 includes an amplifier disposed between the analog switch and the switch circuit portion. The amplifier is configured to have a gain of “1”, a high input impedance, and a low output impedance.
With the conventional AD conversion circuit disclosed in Patent Reference 1, when the analog signal is sampled, the charging time for charging the capacitor of the capacitor element array portion is dependent on the low output impedance of the amplifier, thereby making it possible to reduce the charging time.
Patent Reference 2 has disclosed another conventional AD conversion circuit of a successive approximation type. The conventional AD conversion circuit disclosed in Patent Reference 2 includes a sample hold circuit for sampling an analog input signal; a comparator for sequentially comparing an output voltage of the sample hold circuit with a plurality of analog reference voltages ANs sequentially output from a D/A converter; and a sequential comparison register for storing a comparison result, so that the comparison result is output as a digital output signal Dout.
Further, the conventional AD conversion circuit disclosed in Patent Reference 2 includes a control circuit configured to operate according to a clock signal, so that the control circuit controls a sampling operation and a successive approximation operation.
Further, the conventional AD conversion circuit disclosed in Patent Reference 2 includes a clock signal selection circuit for generating a plurality of clock signals according to a reference clock signal CLK, so that the clock signal selection circuit selects one of the clock signals and outputs to the control circuit as an operation clock signal CLKM.
Further, the conventional AD conversion circuit disclosed in Patent Reference 2 includes a selection control circuit for changing the clock signal selected with the clock signal selection circuit according to the power source voltage, so that the selection control circuit changes a sampling operation time and a successive approximation operation time.
In the conventional technologies disclosed in Patent References 1 and 2, however, it is difficult to automatically set the sampling time according to the value of the input impedance that varies depending on the external device to be connected to the conventional AD conversion circuit according to a usage.
In view of the problems described above, an object of the present invention is to provide an AD conversion circuit, a micro-controller, and a method of adjusting a sampling time. In the present invention, it is possible to automatically set the sampling time according to the value of the input impedance that varies depending on the external device to be connected to the AD conversion circuit according to a purpose.
Further objects and advantages of the invention will be apparent from the following description of the invention.